LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

ENTITY CDRreg_tb IS
END CDRreg_tb;

ARCHITECTURE archCDRreg_tb OF CDRreg_tb IS
	COMPONENT CDRreg IS
		PORT (
			-- '0':start countdown '1':stop countdown
			PCE : IN STD_LOGIC;
			-- '1': stop read and store the countdown number '0':read number
			CDRR : IN STD_LOGIC;
			-- CLOCK signal
			CLK : IN STD_LOGIC;
			-- out data
			CDR : OUT STD_LOGIC
		);
	END COMPONENT;

	SIGNAL PCE, CLK, CDRR, CARRY, CDR : STD_LOGIC;

BEGIN
	UUT : CDRreg PORT MAP(PCE, CDRR, CLK, CDR);
	sim_proc : PROCESS
	BEGIN
		PCE <= '1';

		CDRR <= '0';
		CLK <= '0';
		WAIT FOR 50 ns;

		CLK <= '1';
		WAIT FOR 50 ns;
		PCE <= '0';
		CDRR <= '1';
		CLK <= '0';
		WAIT FOR 50 ns;
		CLK <= '1';
		WAIT FOR 50 ns;
		CLK <= '0';
		WAIT FOR 50 ns;
		CLK <= '1';
		WAIT FOR 50 ns;

		CLK <= '0';
		WAIT FOR 50 ns;
		CLK <= '1';
		WAIT FOR 50 ns;
		WAIT;
	END PROCESS;
END archCDRreg_tb;